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datasheet femtoclock ? ng crystal-to-lvcmos/lvttl clock synthesizer ICS840N051I ics840n051bgi revision a october 14, 2013 1 ?2013 integrated device technology, inc. general description the ICS840N051I is a lvcmos/lvt tl clock synthesizer designed for sdh/sonet and ethernet applications. the device generates a selectable 155.52mhz or 77.76mhz clock signal with excellent phase jitter performance. the device uses idt?s fourth generation femtoclock ? ng technology for an optimum of high clock frequency, low phase noise performance a nd low power consumption.the device supports 2.5v or 3.3v voltage supply and is packaged in a small, lead-free (rohs 6) 8-lead tssop package. the extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. features ? fourth generation femtoclock ? ng technology ? 155.52mhz output clock synthesized from a 19.44mhz fundamental mode crystal ? one 2.5v or 3.3v lvcmos/lvttl clock output ? crystal interface designed for a 12pf parallel resonant crystal ? rms phase jitter @ 155.52mhz, using a 19.44mhz crystal (12khz - 20mhz): 0.482ps (maximum) ? rms phase jitter @ 156.25mhz, using a 19.53125mhz crystal (1.875mhz - 20mhz): 0.138ps (maximum) ? lvcmos interface levels for the control inputs ? full 2.5v or 3.3v supply voltage ? lead-free (rohs 6) packaging ? -40c to 85c ambient operating temperature oe function table note: oe is an asynchronous control freq_sel frequency table note: freq_sel is an asynchronous control. input output enable oe 0 output q is disabled in high-impedance state 1 (default) output q is enabled. input output frequency freq_sel f xtal = 19.2mhz f xtal = 19.44mhz f xtal = 19.53125mhz 0 (default) 153.6mhz 155.52mhz 156.25mhz 1 76.8mhz 77.76mhz 78.125mhz block diagram pin assignment ICS840N051I 8-lead tssop 4.40mm x 3.0mm x 0.925mm package body g package top view 8 vdd 7 q 6 gnd 5 freq_sel vdda 1 oe 2 xtal_out 3 xtal_in 4 pulldown osc xtal_in xtal_out freq_sel oe 32 4, 8 pfd & lpf femtoclock ? ng vco 490-637.5mhz q pullup
ics840n051bgi revision a october 14, 2013 2 ?2013 integrated device technology, inc. ICS840N051I data sheet femtoclock? ng crystal-to-lvcmos/lvttl clock synthesizer pin descriptions and characteristics table 1. pin descriptions note: pulldown and pullup refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1v dda power analog power supply. 2 oe input pullup output enable pin. lvcmos interface levels. 3, 4 xtal_out, xtal_in input crystal oscillator interface. xtal_in is the input, xtal_out is the output. 5 freq_sel input pulldown frequency select pin. lvcmos interface levels. 6 gnd power power supply ground. 7 q output single-ended clock output. lvcmos/lvttl interface levels. 8v dd power core supply pin. symbol parameter test conditio ns minimum typical maximum units c in input capacitance oe, freq_sel 3.5 pf c pd power dissipation capacitance v dd = 3.465v 11 pf v dd = 2.625v 9 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? r out output impedance v dd = 3.3v 15 ? v dd = 2.5v 19 ?
ics840n051bgi revision a october 14, 2013 3 ?2013 integrated device technology, inc. ICS840N051I data sheet femtoclock? ng crystal-to-lvcmos/lvttl clock synthesizer absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operati on of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 3a. power supply dc characteristics, v dd = 3.3v5% or 2.5v5%, t a = -40c to 85c table 3b. lvcmos/lvttl dc characteristics, v dd = 3.3v5% or 2.5v5%, t a = -40c to 85c note 1: output terminated with 50 ? to v dd / 2. see parameter measurement information section, lvcmos output load test circuit diagrams. item rating supply voltage, v dd 3.63v inputs, v i xtal_in other inputs 0v to 2v -0.5v to v dd + 0.5v outputs, v o -0.5v to v dd + 0.5v package thermal impedance, ? ja 117c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 2.375 3.3 3.465 v v dda analog supply voltage v dd ? 0.18 3.3 v dd v v dda analog supply voltage v dd ? 0.18 2.5 v dd v i dda analog supply current 18 ma i dd power supply current 67 ma symbol parameter test conditions minimum typical maximum units v ih input high voltage v dd = 3.3v 2 v dd + 0.3 v v dd = 2.5v 1.7 v dd + 0.3 v v il input low voltage freq_sel v dd = 3.3v -0.3 0.5 v oe v dd = 3.3v -0.3 0.8 v freq_sel v dd = 2.5v -0.3 0.5 v oe v dd = 2.5v -0.3 0.7 v i ih input high current freq_sel v dd = v in = 3.465v or 2.625v 150 a oe v dd = v in = 3.465v or 2.625v 5 a i il input low current freq_sel v dd = 3.465v or 2.625v, v in = 0v -5 a oe v dd = 3.465v or 2.625v, v in = 0v -150 a v oh output high voltage; note 1 q v dd = 3.465v 2.6 v v dd = 2.625v 1.8 v v ol output low voltage; note 1 qv dd = 3.465v or 2.625v 0.5 v
ics840n051bgi revision a october 14, 2013 4 ?2013 integrated device technology, inc. ICS840N051I data sheet femtoclock? ng crystal-to-lvcmos/lvttl clock synthesizer table 4. crystal characteristics ac characteristics table 5. ac characteristics, v dd = v dda = 3.3v5% or 2.5v5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: characterized with 19.2mhz, 19.44mhz and 19.53125mhz crystals. note 1: please refer to the phase noise plots. parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 15.31 19.44 19.92 mhz equivalent series resistance (esr) 80 ? shunt capacitance 7pf capacitive load (cl) 12 pf symbol parameter test conditions minimum typical maximum units f out output frequency freq_sel = 0 122.5 155.52 159.38 mhz freq_sel = 1 61.25 77.76 79.69 mhz t jit(?) rms phase jitter (random); note 1 f out = 155.52mhz, integration range: 12khz ? 20mhz, 19.44mhz crystal 0.350 0.482 ps f out = 77.76mhz, integration range: 12khz ? 20mhz, 19.44mhz crystal 0.354 0.508 ps f out = 156.25mhz, integration range: 1.875mhz ? 20mhz, 19.353125mhz crystal 0.101 0.138 ps ? n single-side band noise power f out = 156.25mhz, offset: 10hz -43.6 dbc/hz f out = 156.25mhz, offset: 100hz -74.1 dbc/hz f out = 156.25mhz, offset: 1khz -107.3 dbc/hz f out = 156.25mhz, offset : 10khz -124.4 dbc/hz f out = 156.25mhz, offset: 100khz -128.9 dbc/hz f out = 156.25mhz, offset: 1mhz -139.1 dbc/hz f out = 156.25mhz, offset: 10mhz -156.7 dbc/hz t r / t f output rise/fall time 20% to 80% 200 600 ps odc output duty cycle 48 52 %
ics840n051bgi revision a october 14, 2013 5 ?2013 integrated device technology, inc. ICS840N051I data sheet femtoclock? ng crystal-to-lvcmos/lvttl clock synthesizer typical phase noise at 77.76mhz typical phase noise at 155.52mhz noise power(dbc/hz) offset frequency (hz) noise power(dbc/hz) offset frequency (hz)
ics840n051bgi revision a october 14, 2013 6 ?2013 integrated device technology, inc. ICS840N051I data sheet femtoclock? ng crystal-to-lvcmos/lvttl clock synthesizer typical phase noise at 156.25mhz noise power(dbc/hz) offset frequency (hz)
ics840n051bgi revision a october 14, 2013 7 ?2013 integrated device technology, inc. ICS840N051I data sheet femtoclock? ng crystal-to-lvcmos/lvttl clock synthesizer parameter measureme nt information 2.5v lvcmos/lvttl output load ac test circuit rms phase jitter output duty cycle/pulse width/period 3.3v lvcmos/lvttl output load ac test circuit output rise/fall time scope qx gnd v dd 1.25v 5% -1.25v 5% v dda 1.25v 5% t period t pw t period odc = v dd 2 x 100% t pw q scope qx gnd v dd 1.65v 5% -1.65v 5% v dda 1.65v 5% q 20% 80% 80% 20% t r t f
ics840n051bgi revision a october 14, 2013 8 ?2013 integrated device technology, inc. ICS840N051I data sheet femtoclock? ng crystal-to-lvcmos/lvttl clock synthesizer applications information overdriving the xtal interface the xtal_in input can be overdriven by an lvcmos driver or by one side of a differential driver through an ac coupling capacitor. the xtal_out pin can be left floating. the amplitude of the input signal should be between 500mv and 1.8v and the slew rate should not be less than 0.2v/ns. for 3.3v lvcmos inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. figure 1a shows an example of the interface diagram for a high speed 3.3v lvcmos driver. this c onfiguration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and changing r2 to 50 ? . the values of the resistors can be increased to reduce the loading for a slower and weaker lvcmos driver. figure 1b shows an example of the interface diagram for an lvpecl driver. this is a standard lvpecl terminati on with one side of the driver feeding the xtal_in input. it is recommended that all components in the schematics be placed in the layout. though some components might not be used, they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. figure 1a. general diagram for lvcmos driver to xtal input interface figure 1b. general diagram for lvpec l driver to xtal input interface vcc xtal_out xtal_in r1 100 r2 100 zo = 50 ohms rs ro zo = ro + rs c1 .1uf lvcmos driver xta l _ o u t xta l _ i n zo = 50 ohms c2 .1uf lvpecl driver zo = 50 ohms r1 50 r2 50 r3 50
ics840n051bgi revision a october 14, 2013 9 ?2013 integrated device technology, inc. ICS840N051I data sheet femtoclock? ng crystal-to-lvcmos/lvttl clock synthesizer schematic layout figure 2 shows an example ICS840N051I application schematic in which the device is operated at v dd = v dda = 3.3v. the schematic example focuses on functional connections and is intended as an example only and may not represent the exact user configuration. refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. for example oe and freq_sel can be configured from an fpga instead of set with pull up and pull down resistors as shown. as with any high speed analog circuitry, the power supply pins are vulnerable to random noise, so to achieve optimum jitter performance isolation of the v dd pin from power supply is required. in order to achieve the best possible filter ing, it is recommended that the placement of the filter components be on the device side of the pcb as close to the power pins as possibl e. if space is li mited, the 0.1f capacitor on the v dd pin must be placed on the device side with direct return to the ground plane though vias. the remaining filter components can be on the opposite side of the pcb. power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. the filter performance is designed for wide range of noise frequencies. this low-pass filter st arts to attenuate noise at approximately 10khz. if a specific frequency noise compone nt is known, such as switching power supply frequencies, it is re commended that component values be adjusted and if required, additi onal filtering be added. additionally, good general design practices for power plane voltage stability suggests adding bulk capacitances in the local area of all devices. figure 2. ICS840N051I application schematic ? 3. 3v c5 0.1uf c4 10uf to lo gi c input pins vdd vdd vdd fb1 blm18bb221sn1 1 2 ru2 not install ru1 1k pl ace 0 .1uf byp ass ca ps di rect ly ad jacen t to the re spect ive vdd and vd da pi ns. r3 33 rd2 1k c3 0.1uf freq_sel to lo gi c in pu t pi ns oe zo = 50 ohm rd1 not i nstall lvcmos receiver s et l ogic input to '1' s et logi c input to '0' log ic contro l inp ut e xamp les u1 vdd a 1 oe 2 xt a l _ o u t 3 xt a l _ i n 4 vdd 8 q 7 gnd 6 freq_sel 5 vdda r1 10 c6 10uf c7 0. 1u f vdd a vdd c2 5pf c1 5pf x1 19.44mhz (12pf )
ics840n051bgi revision a october 14, 2013 10 ?2013 integrated device technology, inc. ICS840N051I data sheet femtoclock? ng crystal-to-lvcmos/lvttl clock synthesizer power considerations this section provides information on power dissipati on and junction temperature for the ICS840N051I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS840N051I is the sum of the core power plus the analog power plus the power dissipated in to the load. the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. ? power (core) max = v dd_max * (i dd + i dda ) = 3.465v *(67ma + 18ma) = 294.53mw ? output impedance r out current due to loading 50 ? to v dd /2 output current i out = v dd_max / [2 * (50 ? + r out )] = 3.465v / [2 * (50 ? + 15 ? )] = 26.7ma ? power dissipation on the r out per lvcmos output power (r out ) = r out * (i out ) 2 = 15 ? * (26.7ma) 2 = 10.7mw per output ? total power (r out ) = 10.7mw * 1 = 10.7mw dynamic power dissipation at 156.25mhz power (156.25mhz) = c pd * frequency * (v dd ) 2 = 11pf * 156.25mhz * (3.465v) 2 = 20.64mw per output total power (156.25mhz) = 20.64mw * 1 = 20.64mw total power dissipation ? total power = power (core) max + power (r out ) + power (156.25mhz) = 294.53mw + 10.7mw + 20.64mw = 325.87mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance q ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 117c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.326w *117c/w = 123.2c. th is is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ? ja for 8 lead tssop, forced convection ? ja by velocity meters per second 0 multi-layer pcb, jedec standard test boards 117c/w
ics840n051bgi revision a october 14, 2013 11 ?2013 integrated device technology, inc. ICS840N051I data sheet femtoclock? ng crystal-to-lvcmos/lvttl clock synthesizer reliability information table 7. ? ja vs. air flow table for a 8-lead tssop transistor count the transistor count for ICS840N051I is: 24,811 package outline and package dimensions p ackage outline - g suffix for 8 lead tssop table 8. package dimensions reference document: jedec publication 95, mo-153 ? ja vs. air flow meters per second 0 multi-layer pcb, jedec standard test boards 117c/w all dimensions in millimeters symbol minimum maximum n 8 a 1.20 a1 0.5 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 2.90 3.10 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 ? 0 8 aaa 0.10
ics840n051bgi revision a october 14, 2013 12 ?2013 integrated device technology, inc. ICS840N051I data sheet femtoclock? ng crystal-to-lvcmos/lvttl clock synthesizer ordering information table 9. ordering information part/order number marking package shipping packaging temperature 840n051bgilf 51bil lead-free, 8-lead tssop tube -40 ? c to 85 ? c 840n051bgilft 51bil lead-free, 8-lead tssop tape & reel -40 ? c to 85 ? c
ics840n051bgi revision a october 14, 2013 13 ?2013 integrated device technology, inc. ICS840N051I data sheet femtoclock? ng crystal-to-lvcmos/lvttl clock synthesizer revision history sheet rev table page description of change date a 1 general description - corrected output frequ ency of 156.25mhz to 155.52mhz in second sentence. 10/14/2013
disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in applications involving extreme environmenta l conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to signifi- cantly affect the health or safety of users. anyone using an id t product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2013. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support sales netcom@idt.com +480-763-2056 we?ve got your timing solution ICS840N051I data sheet femtoclock? ng crystal-to-lvcmos/lvttl clock synthesizer

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